In the past decade, there has been a dramatic increase both in processor speeds and in memory capacity. As a result, the need for networks to handle high-speed transfer of large quantities of data among devices has also increased. Transceivers capable of efficiently receiving and transmitting high-speed data are critical components of these high-speed networks.
To reliably process a received data signal, a receiver must match its operating characteristics to the characteristics of the received data signal. For example, to minimize data recovery errors, a receiver generates a clock signal to sample the received data signal at times that produce optimal data recovery. To achieve this optimal data recovery, the receiver must lock the sampling clock to the clock of the data transmitter. A clock and data recovery (CDR) circuit in the receiver is a typical circuit used to recover the transmission clock from the received data signal.
Many conventional analog CDR circuits use an analog phase-locked loop (PLL) for frequency and phase acquisition. Analog PLL circuits typically include a phase detector, loop filter, and voltage controlled oscillator (VCO) connected in series. The output of the VCO (i.e., recovered clock) is fed back as an input to the phase detector. The phase detector compares the phase of the input data signal to the phase of the recovered clock and generates an output signal indicative of the phase difference.
These analog PLL circuits have several limitations. Because the circuits typically are implemented using a high order loop and have a loop gain that depends upon the signal transition density, analog PLL circuits are susceptible to instability. Also, because these circuits have unrestrained frequency acquisition characteristics, the circuit may falsely lock to spurious tones and harmonics of the data signal. To address these issues, analog PLL circuits are often implemented using complex circuitry to aid frequency acquisition.
Other conventional CDR circuits use an analog delay-locked loop (DLL) for frequency and phase acquisition. Analog DLL circuits typically include a phase detector (e.g., a Hogge detector), loop filter, and an analog controlled variable delay module consisting of delay elements connected in series. The analog controlled variable delay module receives inputs from a local frequency source and the loop filter. The delay module then produces an output signal (i.e., recovered clock) that is fed back as an input to the phase detector. Because the characteristics of the delay module vary with process, temperature, and supply voltage variations, this type of DLL is difficult to design for mass production and thus, has a limited range of applications.
In addition, analog implementations that allow different loop bandwidths in the acquisition and tracking phase require more complexity than the conventional analog CDRs described above and are still susceptible to degradations caused by process, temperature and voltage variation.
Many conventional digital CDR circuits use a digital DLL including a binary phase detector (also referred to as a ‘bang—bang’ type phase detector), a phase accumulator, and a phase adjustment element connected in series. These digital CDR circuits are typically used in applications where the synchronization or training sequence preceding transmission of the data payload is long and consists of many cycles. Because the binary phase detector has a high detection gain, a sufficiently small loop bandwidth must be used to prevent large phase jumps in the recovered clock. In the tracking phase, this small loop bandwidth is desirable for rejecting or filtering high frequency cycle-to-cycle type jitter. However, a small loop bandwidth also means a slow response time during the acquisition phase. A slow response time during acquisition limits the use of these DLL circuits in applications where the synchronization sequence preceding the data is restrictively short.
A common implementation of the phase adjustment element of the conventional DLL described above uses tapped delay lines. The overall delay of the circuit is set by a multiplexer that selects one of the delay outputs as the recovered clock. In these implementations, because the phase of the delayed signal cannot be fed back, this type of DLL is restricted to a limited frequency and phase capture range of operation. This limitation is further exacerbated by the fact that the delay in each element varies with temperature, process variation, and power supply voltage. Thus, the ability to obtain adequate phase and frequency capture is made increasingly difficult. Also, for a long tapped delay line, jitter is accumulated as the signal is passed through the numerous delay elements. Thus, if the last few tapped delay lines are used, high self-induced jitter results.
Another potential limitation of using conventional digital or analog CDR circuits, such as those described above, is the possibility that a state could occur such that the phase of the recovered clock is not moved in any direction (referred to as a “dead state” or “meta-stability condition”). A dead state could occur when the synchronization sequence has jitter and duty clock distortion and the clock is not aligned correctly. This effect is undesirable in systems where the number of synchronizations cycles is small and fast acquisition or locking response is required.
Therefore, a need exists for a clock and data recovery system that can detect and rapidly mitigate meta-stability conditions.
A further need exists for a clock and data recovery system that can provide time-varying adjustment of the system gain.